Nanosheet devices can be viable device options instead of fin field-effect transistors (FinFETs). For example, nanowires or nanosheets can be used as the fin structure in a dual-gate, tri-gate or gate-all-around (GAA) FET device. Complementary metal-oxide semiconductor (CMOS) scaling can be enabled by the use of stacked nanowires and nanosheets, which offer superior electrostatics and higher current density per footprint area than FinFETs. Additionally, nanosheet devices are being pursued as a viable device option for the 5 nm node and beyond. Nanosheet formation relies on the selective removal of one semiconductor (e.g., Si) with respect to another (SiGe) to form the nanosheet and GAA structures. However, in existing approaches, the epitaxy grows bottom-up and from the nanosheets at the side walls, creating a parasitic device under the nanosheet stack. Accordingly, there is a need for avoiding such bottom-up epitaxial growth of nanosheet source/drain regions.